PWMEN0=CT32BN_MAT0_IS_CONTR, PWMEN2=CT32BN_MAT2_IS_CONTR, PWMEN3=CT32BN_MAT3_IS_CONTR, PWMEN1=CT32BN_MAT01_IS_CONT
PWM Control Register. The PWMCON enables PWM mode for the external match pins CT32Bn_MAT[3:0].
| PWMEN0 | PWM mode enable for channel0. 0 (CT32BN_MAT0_IS_CONTR): CT32Bn_MAT0 is controlled by EM0. 1 (PWM_MODE_IS_ENABLED_): PWM mode is enabled for CT32Bn_MAT0. |
| PWMEN1 | PWM mode enable for channel1. 0 (CT32BN_MAT01_IS_CONT): CT32Bn_MAT01 is controlled by EM1. 1 (PWM_MODE_IS_ENABLED_): PWM mode is enabled for CT32Bn_MAT1. |
| PWMEN2 | PWM mode enable for channel2. 0 (CT32BN_MAT2_IS_CONTR): CT32Bn_MAT2 is controlled by EM2. 1 (PWM_MODE_IS_ENABLED_): PWM mode is enabled for CT32Bn_MAT2. |
| PWMEN3 | PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle. 0 (CT32BN_MAT3_IS_CONTR): CT32Bn_MAT3 is controlled by EM3. 1 (PWM_MODE_IS_ENABLED_): PWM mode is enabled for CT132Bn_MAT3. |
| RESERVED | Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. |